1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to semiconductor memory devices having a function of initializing storage data of memory cells.
2. Description of the Background Art
At present, semiconductor memory devices such as RAMs (Random Access Memories) are incorporated into a single chip for use in various semiconductor integrated circuits or in various fields as units. Memory arrays of some of such semiconductor memory devices must be set to a predetermined storage data pattern (initialized) depending on their usages when a power is applied (at the start of the use) in an actual use. One example of such semiconductor memory devices is a cache memory or a matching memory. A cache memory is a memory operating at a very high speed for use in transferring and storing storage data of a main memory device. A matching memory includes memory storing identifiers which perform various data processing according to these identifiers in a computer system such as a data flow processor requiring the same. In a semiconductor memory device requiring such "initialization of data", the storage data of all the memory cells or part of the memory cells (for example in a case of a cache memory, memory cells of addresses storing identifiers) in a memory array is set to a logical value "1" or a logical value "0" in this initialization.
FIG. 14 is a schematic block diagram showing one example of an entire arrangement of a conventional SRAM (Static Random Access Memory) having a function of performing such initialization. Referring to FIG. 14, the SRAM includes a memory array 1b of a plurality of blocks each having memory cells for storing input data arranged in a matrix of rows and columns, a data input/output terminal T.sub.D for receiving input data and output data, a row address input terminal Ar for receiving an external row address signal which selects a row of a block in memory array 1b, a column address input terminal Ac for receiving an external column address signal which selects a column of a block in memory array 1b and a block address input terminal 1b for receiving an external block address selecting signal which selects a block in memory array 1b.
FIG. 15 is a circuit diagram showing an internal arrangement of memory array 1b. FIG. 9 shows a representation of memory cell columns in an arbitrary block.
Referring to FIG. 15, a memory cell MC is connected between two paired bit lines BIT and BIT.
The memory cell MC includes two inverters INV1 and INV2 connected in anti-parallel, an N channel MOS transistor TR1 connected between the input end of inverter INV2 and the bit line BIT and an N channel MOS transistor TR2 connected between the input terminal of inverter INV1 and the other bit line BIT. Both of the gates of transistors TR1 and TR2 are connected to the same word line WL. The word line WL is connected to a row decoder 3 and the paired bit lines BIT and BIT are connected to a I/O circuit 6 in FIG. 14.
I/O circuit 6 forms a path for transferring the data read from memory array 1b to an output buffer 9 and a path for transferring the data to be written in memory array 1b from an input data control circuit 10 to memory array 1b. The former path includes a sense amplifier for amplifying data read from memory array 1b.
In data writing, row address buffer 2 accepts a row address signal applied to row address input terminal Ar.
Then, row decoder 3 decodes the row address signal accepted by row address buffer 2 to selectively render data writable/readable in the memory cells in one row corresponding to the row address designated by the row address signal.
That is, row decoder 3 applies a "H" (logical high) level voltage to the word line WL (see FIG. 15) corresponding to the row of the memory cells designated by the row address signal. As a result, transistors TR1 and TR2 are turned on in all the memory cells connected to the word line WL for attaining the "H" level, and thereby electrically connecting all the memory cells to the corresponding bit line pairs of BIT and BIT.
At the same time, a block address signal applied to block address input terminal 1b is accepted by a block address buffer 7. Then, a block decoder 8 decodes the block address signal accepted by block address buffer 7 to select all the bit line pairs corresponding to one block designated by the accepted block address signal in I/O circuit 6. That is, block decoder 8 selects one block from among the blocks in memory array 1a.
Similarly, a column address signal applied to column address input terminal Ac is accepted by a column address buffer 4. Then, a column decoder 5 decodes the column address signal accepted by column address buffer 4 to selectively enable only the data transmission to the memory cells of one column corresponding to the column address designated by the column address signal out of the memory cells in the block selected by block decoder 8. In other words, column decoder 5 electrically connects only the bit line pair corresponding to the column designated by the column address signal with input data control circuit 10 in I/O circuit 6 out of the bit line pairs of BIT and BIT in the selected block connected to I/O circuit 6. That is, column decoder 5 selects one pair from among the bit line pairs in memory array 1b.
Meanwhile, an input buffer 11 accepts each bit signal of the data applied to data input/output terminal T.sub.D and applies the same to input data control circuit 10 in the data writing. In ordinary data writing other than data writing for "initialization", input data control circuit 10 applies the data applied from input buffer 11 to I/O circuit 6. In I/O circuit 6, however, input data control circuit 10 is electrically connected to only the bit line pair corresponding to the memory cell column selected by column decoder 5 as described above. Then, I/O circuit 6 applies the data supplied from input data control circuit 10 as signals of complementary level voltages to the bit line pair of BIT and BIT of FIG. 15, respectively. More specifically, all the transistors TR1 and TR2 are turned on in memory array 1b, and each of the transistors has a gate connected to one word line (selected word line) WL supplied with a "H" level potential by row decoder 3.
In addition, I/O circuit 6 applies a potential of a logical value corresponding to the data applied from input data control circuit 10 and an inversion potential thereof to two bit lines BIT and BIT constituting the bit line pair selected by column decoder 5, respectively. As a result, the potential applied to the corresponding bit line BIT is supplied to inverter INV1 through transistor TR2 in the memory cell arranged at the cross-over point between the column selected by column decoder 5 and the row selected by row decoder 3, with reference to FIG. 15. Inverter INV1 inverts that potential and outputs the inverted potential to inverter INV2. Inverter INV2 is supplied with a potential of an opposite level to the input potential of inverter INV from the other bit line BIT through transistor TR1. In this memory cell, therefore, the nodes between inverters INV1 and INV2 are fixed to the potential applied to bit line BIT and corresponding to the inverse logical value to the input data and the potential applied to bit line BIT and corresponding to the input data. That is, the input data is written in this memory cell.
Thereafter, row decoder 3 lowers the potential on the word line WL corresponding to this memory cell to a "L" level. As a result, the transistors TR1 and TR2 are turned off in all the memory cells connected to the selected word line WL including this memory cell. However, the respective outputs of inverters INV1 and INV2 are fed back to their inputs, so that the potentials at the nodes between inverters INV1 and INV2 are maintained at the level in the data writing. That is, the written data is stored in this memory cell. A node to be maintained at a potential corresponding to data such as the node between inverters INV1 and INV2 is referred to as storage data hereinafter.
The data input from data input/output terminal T.sub.D is written and stored in this way in the memory cell arranged at the cross-over point between the column designated by the column address signal and the row designated by the row address signal in the block designated by the block address signal out of the blocks in memory array 1b.
FIG. 16 is a circuit diagram showing in more detail the respective arrangements of a memory cell included in memory array 1b shown in FIG. 14. Referring to FIG. 16, each memory cell MC in memory array 1b includes the above-described transistors TR1 and TR2, two P channel MOS transistors 210 and 220 and two N channel MOS transistors 230 and 240. Transistors 210 and 230 are connected in series between a power supply Vcc and ground GND to constitute inverter INV1. A node n1 between transistors 210 and 230 is the output end of this inverter INV1. Transistors 220 and 240 are also connected in series between power supply Vcc and ground GND to constitute inverter INV2. A node n2 between transistors 220 and 240 is the output end of this inverter INV2. The gate of transistor 210 and the gate of transistor 230 are connected to each other. The gate connection point between transistors 210 and 230 is connected to an output end n2 of inverter INV2 as the input end of inverter INV1. The gate of transistor 220 and the gate of transistor 240 are also connected to each other. The gate connection point between transistors 220 and 240 is connected to output end n1 of inverter INV1 as the input end of inverter INV2.
In data reading, row address buffer 2 and row decoder 3, column address buffer 4 and column decoder 5, and block address buffer 7 and block decoder 8 operate similarly to those in the data writing, for thereby rendering data writable/readable only the memory cell selected by the block address signal, the column address signal and row address signal out of the memory cells in memory array 1b.
In other words, referring to FIG. 15, the transistors TR1 and TR2 are turned on and the corresponding bit line pair of BIT and BIT is electrically connected to output buffer 9 through I/O circuit 6, in one memory cell corresponding to the word line WL supplied with a "H" level potential by row decoder 3 and corresponding to the bit line pair selected by column decoder 5 in the block selected by block decoder 8. Upon the turning-on of transistors TR1 and TR2, the potentials on the corresponding bit line pair of BIT and BIT change in response to the potentials at the connection points, that is, the storage nodes, between inverters INV1 and INV2. In other words, the storage data of the selected memory cell is read onto the corresponding bit line pair. The potential change of this bit line pair of BIT and BIT is sensed/ amplified by a sense amplifier in I/O circuit 6, and converted to the potential corresponding to the storage data and then applied to output buffer 9. Output buffer 9 outputs the potential corresponding to this storage data as the read data to data input/output terminal T.sub.D.
In actuality, a chip and input/output control circuit 13 controls an operation timing of row address buffer 2, column address buffer 4, block address buffer 7, output buffer 9 and input buffer 11 such that the SRAM operates in data writing and reading in such a manner as described above.
This control circuit 13 carries out this controlling based on a chip enable signal externally applied to a chip enable terminal CE, a write enable signal externally applied to a write enable terminal WE and an output enable signal externally applied to an output enable terminal OE. The chip enable signals is for selecting a chip to be operated at present in the device containing this SRAM chip and the signal attains a "L" level when this SRAM chip should be operated. A write enable signal is for indicating whether this memory cell should be set at a data writing mode at present or not and attains a "L" level when this SRAM is set at the data writing mode. An output enable signal is for indicating whether or not the read data should be output from this SRAM at present and the signal attains a "L" level when the read data should be output.
Control circuit 13 activates the operations of row address buffer 2, column address buffer 4 and block address buffer 7 in a period when this SRAM chip should be operated, and the period when a chip enable signal is at a "L" level. Control circuit 13 activates input buffer 11 in a period in which data should be written in this memory, and the period when a write enable signal is at a "L" level, such that the data applied to input/output terminal T.sub.D is taken into the SRAM. Control circuit 13 activates output buffer 9 such that the read data from memory array 1b is externally output in a period when the read data should be output, and the period when an output enable signal is at a "L" level.
The foregoing operation of this SRAM is the same as that of an ordinary SRAM without an initialization function.
This SRAM shown in FIG. 14, however, includes an initialization data control circuit 12, a clock generation circuit 14 and an initialization address generating circuit 15 in addition to the function part provided in such an ordinary SRAM as described above.
Initialization address generating circuit 15 generates a block address signal, a row address signal and a column address signal indicative of a block address, a row address and a column address, respectively, corresponding to the address of a predetermined memory cell to be initialized and applies the same to block decoder 8, column decoder 5 and row decoder 3, respectively.
Initialization data control circuit 12 generates predetermined data (initialization data) to be applied to the memory cell to be initialized at initialization and applies the same to input data control circuit 10.
Clock generation circuit 14 generates clock signals for controlling initialization address generation circuit to generate a block address signal, a row address signal and a column address signal and for controlling initialization data control circuit 12, to generate initialization data, based on control signals (initialization signals) for initialization externally applied to an initialization signal input terminal T.sub.1.
An initialization signal is applied to initialization signal input terminal T.sub.1 at the application of power. Clock generation circuit 14 generates the above-described clock signal in response to this initialization signal. Then, initialization data control circuit 12 and initialization address generation circuit 15 operate as described above in response to this clock signal. In such initialization, input buffer 11 which accepts external input data, is still disabled by control circuit 13, whereby input data control circuit 10 receives none of ordinary data to be written as an input but applies the data supplied from initialization data control circuit 12 as data to be written to I/O circuit 6. Similarly, at this time, row address buffer 2, column address buffer 4 and block address buffer 7 are still disabled by column circuit 13 at this time, whereby row decoder 3, column decoder 5 and block decoder 8 receive none of the external input address signals. At the initialization, therefore, row decoder 3, column decoder 5 and block decoder 8 receive only the row address signal, column address signal and block address signal applied from initialization address generation circuit 15, respectively, and decode the same. In this case therefore, memory cells to be initialized are sequentially selected on an address basis in memory array 1b, so that the initialization data generated by generation data control circuit 12 is written thereto.
Initialization data control circuit 12 and initialization address generation circuit 15 may directly receive necessary clocks as inputs.
As described in the foregoing, in this semiconductor memory device the storage data of a predetermined memory cell is initialized by a circuit for initialization additionally provided in the device, that is, by means of the hardware, at the power on. The circuit for initialization, that is, initialization data control circuit 12, clock generation circuit 14 and initialization address generation circuit 15 is incorporated in this semiconductor memory device beforehand. Thus, the address signal generated from the initialization is uniform, making it impossible to initialize memory cells of different addresses at each initialization and to initialize the data of memory cells to different data at each initialization. Therefore, initialization is not performed by means of hardware but initialization is generally carried out by software for such irregular initialization as this.
Initialization by software performs initialization by using software such as a program in the system including a semiconductor memory device for example. More specifically, the system, supplied with a program for initialization to generate addresses and data, generates by itself the addresses to be initialized and initialization data outside the semiconductor memory device and applies the same to the semiconductor memory device by executing the program. Then, the semiconductor memory device operates similarly to that in ordinary data writing to write the generated data in the generated addresses. Such initialization requires none of such circuits for initialization in the semiconductor memory device as described previously. That is, the semiconductor memory device performs an operation of writing given data in given addresses both in data writing for initialization and in ordinary data writing. In this case, of course a mode setting instruction for setting the semiconductor memory device to operate in a writing mode, when write addresses and write data to be applied to the semiconductor memory device for initialization should be written in the program or the like.
In the initialization by hardware, when the data bit to be initialized is fixed irrespective of address and the addresses of the memory cell which storage data should be initialized are regular such as all the addresses, all the even-numbered addresses, all the odd-numbered addresses and the serial addresses from address 0 to a predetermined address in the memory array and the initialization data to be written is also regular data that it is the same for each address, initialization data control circuit 12, clock generation circuit 14 and initialization address generation circuit 15 of FIG. 14 can be achieved by circuits of relatively simple structure. However, if the data bit to be initialized, the address to be initialized and the initialization data to be written and the like are irregular, these circuits for initialization are made complicated. For example, initialization address generation circuit 15 is a circuit for generating an address signal by counting clocks from clock generation circuit 14 which includes a counter for carrying out this counting. If the address to be generated is irregular, complicated control is required of the counting operation of this counter. Thus, a complicated address to be initialized results in a complicated arrangement of initialization address generation circuit 15. As a result, execution of the complication initialization requires an increased circuit for initialization in scale, for thereby making it impossible to provide these circuits in the semiconductor memory device. In such a case, these circuit portions should be structured separately from the semiconductor memory device. For this reason, complicated initialization is generally performed by software as described above.
As shown in the foregoing, initialization of storage data of a semiconductor memory device conventionally includes that by means of hardware and that by software.
In the former case, a time period required for initialization depends on a time required for the circuits for initialization (initialization data control circuit 12, clock generation circuit 14 and initialization address generation circuit 15 of FIG. 14) provided in the semiconductor memory device to generate addresses and data and to write all the generated data in all the generated addresses. In the latter case, a time period required for initialization depends on a time period required for the system containing the semiconductor memory device to carry out the program for initialization. However, writing of the initialization data is carried out by an ordinary writing operation of the semiconductor memory device in both cases.
In such a semiconductor memory device as a SRAM, addresses in which data is written are sequentially selected one by one and the corresponding data is written in one of these selected addresses in a data writing as described above. Therefore, data cannot be written simultaneously in a plurality of addresses. The time required for writing the initial data is accordingly increased as the number of memory cells to be initialized is increased, that is, the number of addresses and data bits to be initialized is increased, which results in the increased time period required for initialization. In recent years semiconductor memory devices have been made large in scale, which is followed by the increased number of memory cells to be initialized. As a result, such a conventional initialization method makes an initialization time period longer and consequently decreases an operational speed of a semiconductor device, which results in a reduced operational speed of a system containing the device.
In initializing storage data of a semiconductor memory device by means of hardware as described above, the execution of complicated initialization requires large additional circuits. Such additional circuits require more power to be consumed and an increase in a chip area results, which are not preferable in view of low power consumption and miniaturization of a semiconductor integrated circuit device. Such complicated initialization by means of software also makes the program complicated to increase an execution time due to the increased program size, which results in an increase in initialization time.